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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">cy_stc_fll_manual_config_t Struct Reference<div class="ingroups"><a class="el" href="group__group__sysclk.html">SysClk       (System Clock)</a> &raquo; <a class="el" href="group__group__sysclk__fll.html">Frequency Locked Loop (FLL)</a> &raquo; <a class="el" href="group__group__sysclk__fll__structs.html">Data Structures</a></div></div>  </div>
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<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>Structure containing information for manual configuration of FLL. </p>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a93a7114899568aa34c09a288957086fc"><td class="memItemLeft" align="right" valign="top"><a id="a93a7114899568aa34c09a288957086fc"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__fll__manual__config__t.html#a93a7114899568aa34c09a288957086fc">fllMult</a></td></tr>
<tr class="memdesc:a93a7114899568aa34c09a288957086fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG register, FLL_MULT bits. <br /></td></tr>
<tr class="separator:a93a7114899568aa34c09a288957086fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab73af796ba57ad3390812c67866ac80a"><td class="memItemLeft" align="right" valign="top"><a id="ab73af796ba57ad3390812c67866ac80a"></a>
uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__fll__manual__config__t.html#ab73af796ba57ad3390812c67866ac80a">refDiv</a></td></tr>
<tr class="memdesc:ab73af796ba57ad3390812c67866ac80a"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG2 register, FLL_REF_DIV bits. <br /></td></tr>
<tr class="separator:ab73af796ba57ad3390812c67866ac80a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a38e85bdd8e8189823706aaae0711d6cd"><td class="memItemLeft" align="right" valign="top"><a id="a38e85bdd8e8189823706aaae0711d6cd"></a>
<a class="el" href="group__group__sysclk__fll__enums.html#gac8760ee841ca24255c9a4fee494b79aa">cy_en_fll_cco_ranges_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__fll__manual__config__t.html#a38e85bdd8e8189823706aaae0711d6cd">ccoRange</a></td></tr>
<tr class="memdesc:a38e85bdd8e8189823706aaae0711d6cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG4 register, CCO_RANGE bits. <br /></td></tr>
<tr class="separator:a38e85bdd8e8189823706aaae0711d6cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0791fc7e856b2669453d9910e59978e5"><td class="memItemLeft" align="right" valign="top"><a id="a0791fc7e856b2669453d9910e59978e5"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__fll__manual__config__t.html#a0791fc7e856b2669453d9910e59978e5">enableOutputDiv</a></td></tr>
<tr class="memdesc:a0791fc7e856b2669453d9910e59978e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG register, FLL_OUTPUT_DIV bit. <br /></td></tr>
<tr class="separator:a0791fc7e856b2669453d9910e59978e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a99a5cde7d712e279f423ec34bac38ba7"><td class="memItemLeft" align="right" valign="top"><a id="a99a5cde7d712e279f423ec34bac38ba7"></a>
uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__fll__manual__config__t.html#a99a5cde7d712e279f423ec34bac38ba7">lockTolerance</a></td></tr>
<tr class="memdesc:a99a5cde7d712e279f423ec34bac38ba7"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG2 register, LOCK_TOL bits. <br /></td></tr>
<tr class="separator:a99a5cde7d712e279f423ec34bac38ba7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acffd4fd78b822b843d2d050b8de24399"><td class="memItemLeft" align="right" valign="top"><a id="acffd4fd78b822b843d2d050b8de24399"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__fll__manual__config__t.html#acffd4fd78b822b843d2d050b8de24399">igain</a></td></tr>
<tr class="memdesc:acffd4fd78b822b843d2d050b8de24399"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG3 register, FLL_LF_IGAIN bits. <br /></td></tr>
<tr class="separator:acffd4fd78b822b843d2d050b8de24399"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afcdb8b94269faa0dd3b304aca6507eca"><td class="memItemLeft" align="right" valign="top"><a id="afcdb8b94269faa0dd3b304aca6507eca"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__fll__manual__config__t.html#afcdb8b94269faa0dd3b304aca6507eca">pgain</a></td></tr>
<tr class="memdesc:afcdb8b94269faa0dd3b304aca6507eca"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG3 register, FLL_LF_PGAIN bits. <br /></td></tr>
<tr class="separator:afcdb8b94269faa0dd3b304aca6507eca"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:add75a5aff415c2167ceabdf7021e8494"><td class="memItemLeft" align="right" valign="top"><a id="add75a5aff415c2167ceabdf7021e8494"></a>
uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__fll__manual__config__t.html#add75a5aff415c2167ceabdf7021e8494">settlingCount</a></td></tr>
<tr class="memdesc:add75a5aff415c2167ceabdf7021e8494"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG3 register, SETTLING_COUNT bits. <br /></td></tr>
<tr class="separator:add75a5aff415c2167ceabdf7021e8494"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a360c2401fd72307f663bdd153fe9a04e"><td class="memItemLeft" align="right" valign="top"><a id="a360c2401fd72307f663bdd153fe9a04e"></a>
<a class="el" href="group__group__sysclk__fll__enums.html#ga777e08424e26c9cd8c2602b2114e716b">cy_en_fll_pll_output_mode_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__fll__manual__config__t.html#a360c2401fd72307f663bdd153fe9a04e">outputMode</a></td></tr>
<tr class="memdesc:a360c2401fd72307f663bdd153fe9a04e"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG3 register, BYPASS_SEL bits. <br /></td></tr>
<tr class="separator:a360c2401fd72307f663bdd153fe9a04e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3f55718d95984c5049016605761ff401"><td class="memItemLeft" align="right" valign="top"><a id="a3f55718d95984c5049016605761ff401"></a>
uint16_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__fll__manual__config__t.html#a3f55718d95984c5049016605761ff401">cco_Freq</a></td></tr>
<tr class="memdesc:a3f55718d95984c5049016605761ff401"><td class="mdescLeft">&#160;</td><td class="mdescRight">CLK_FLL_CONFIG4 register, CCO_FREQ bits. <br /></td></tr>
<tr class="separator:a3f55718d95984c5049016605761ff401"><td class="memSeparator" colspan="2">&#160;</td></tr>
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